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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2022-07-28 14:10:44 +0100 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2022-07-28 14:10:44 +0100 |
| commit | 69d5a038b90d3616a5c22d4e0e682aad4679758d (patch) | |
| tree | 0552de05903aa8a04c1b35edb0de528ca34c364f /lldb/source/Plugins/ScriptInterpreter/Python/SWIGPythonBridge.cpp | |
| parent | 25a83005ef9dfce7c40c295a987f9e0ad7dc76d3 (diff) | |
| download | llvm-69d5a038b90d3616a5c22d4e0e682aad4679758d.zip llvm-69d5a038b90d3616a5c22d4e0e682aad4679758d.tar.gz llvm-69d5a038b90d3616a5c22d4e0e682aad4679758d.tar.bz2 | |
[DAG] Enable ISD::SRL SimplifyMultipleUseDemandedBits handling inside SimplifyDemandedBits
This patch allows SimplifyDemandedBits to call SimplifyMultipleUseDemandedBits in cases where the ISD::SRL source operand has other uses, enabling us to peek through the shifted value if we don't demand all the bits/elts.
This is another step towards removing SelectionDAG::GetDemandedBits and just using TargetLowering::SimplifyMultipleUseDemandedBits.
There a few cases where we end up with extra register moves which I think we can accept in exchange for the increased ILP.
Differential Revision: https://reviews.llvm.org/D77804
Diffstat (limited to 'lldb/source/Plugins/ScriptInterpreter/Python/SWIGPythonBridge.cpp')
0 files changed, 0 insertions, 0 deletions