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| author | Hsiangkai Wang <kai.wang@sifive.com> | 2021-10-07 19:30:33 +0800 |
|---|---|---|
| committer | Hsiangkai Wang <kai.wang@sifive.com> | 2021-10-19 09:30:13 +0800 |
| commit | facff468b6c47b954aebd297c90bd44accaa54c6 (patch) | |
| tree | 66d5f00ced06cecbba0df1ee78245dc504f39b4f /lldb/source/Plugins/ScriptInterpreter/Python/PythonReadline.h | |
| parent | 21bb463e9639719f1aae9535825a40732eda487b (diff) | |
| download | llvm-facff468b6c47b954aebd297c90bd44accaa54c6.zip llvm-facff468b6c47b954aebd297c90bd44accaa54c6.tar.gz llvm-facff468b6c47b954aebd297c90bd44accaa54c6.tar.bz2 | |
[RISCV] Reorder the vector register allocation order.
GPR uses argument registers as the first group of registers to allocate.
This patch uses vector argument registers, v8 to v23, as the first group
to allocate.
Differential Revision: https://reviews.llvm.org/D111304
Diffstat (limited to 'lldb/source/Plugins/ScriptInterpreter/Python/PythonReadline.h')
0 files changed, 0 insertions, 0 deletions