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| author | John Brawn <john.brawn@arm.com> | 2022-09-01 15:58:24 +0100 |
|---|---|---|
| committer | John Brawn <john.brawn@arm.com> | 2022-09-06 11:36:12 +0100 |
| commit | e26cadcc32a2194610963bfe140795e978349ba2 (patch) | |
| tree | 65c93e5e9ffab7347f825f2ea84ac38fa802b917 /lldb/source/Plugins/ScriptInterpreter/Python/PythonReadline.h | |
| parent | 0f2ec35691cd616644497f9802eea2dd0f03323a (diff) | |
| download | llvm-e26cadcc32a2194610963bfe140795e978349ba2.zip llvm-e26cadcc32a2194610963bfe140795e978349ba2.tar.gz llvm-e26cadcc32a2194610963bfe140795e978349ba2.tar.bz2 | |
[ARM] Constant pools need 4-byte alignment if we only have tADR
When the only ADR instruction we have is the 16-bit thumb one then all
constant pool entries need to be 4-byte aligned, as tADR has an offset
that's a multiple of 4.
It looks like previously there happened to be no situations in which
we encountered a constant pool entry with alignment less than 4, so
failing to do this didn't cause any problems, but the expansion of
cttz to a table added by D128911 does use a constant pool with
alignment 1, so we now need to handle it correctly.
Differential Revision: https://reviews.llvm.org/D133199
Diffstat (limited to 'lldb/source/Plugins/ScriptInterpreter/Python/PythonReadline.h')
0 files changed, 0 insertions, 0 deletions