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| author | Sanjay Patel <spatel@rotateright.com> | 2022-01-17 18:23:32 -0500 |
|---|---|---|
| committer | Sanjay Patel <spatel@rotateright.com> | 2022-01-17 18:25:42 -0500 |
| commit | ba6485e25fc56468f34cc8a6938d66d3c5f46596 (patch) | |
| tree | b42f0e847f0027784bc7a0ead209903aa23f5b18 /lldb/source/Plugins/ScriptInterpreter/Python/PythonReadline.h | |
| parent | e965d068e08be3caddf44f8440dd16f29b4fc15b (diff) | |
| download | llvm-ba6485e25fc56468f34cc8a6938d66d3c5f46596.zip llvm-ba6485e25fc56468f34cc8a6938d66d3c5f46596.tar.gz llvm-ba6485e25fc56468f34cc8a6938d66d3c5f46596.tar.bz2 | |
[SDAG] add demanded bits transform for bswap
A possible codegen regression for PowerPC is noted in D117406
because we don't recognize a pattern that demands only 1 byte
from a bswap.
This fold has existed in IR since close to the beginning of LLVM:
https://github.com/llvm/llvm-project/blame/main/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp#L794
...so this patch copies that code as much as possible and adapts
it for SDAG.
The test for PowerPC that would change in D117406 is over-reduced
with undefs, so I recreated it for AArch64 and x86 by passing in
pointer args and renamed the values to make the logic clearer.
Differential Revision: https://reviews.llvm.org/D117508
Diffstat (limited to 'lldb/source/Plugins/ScriptInterpreter/Python/PythonReadline.h')
0 files changed, 0 insertions, 0 deletions