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| author | Craig Topper <craig.topper@sifive.com> | 2024-08-21 20:37:37 -0700 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2024-08-21 20:37:37 -0700 |
| commit | 88636854b007affdbe324369b26c9ded66934b22 (patch) | |
| tree | 995ffe4eb1b065e7b5198e367451651b34cff836 /lldb/source/Plugins/ScriptInterpreter/Python/PythonReadline.h | |
| parent | 796787d07c30cb9448e1f9ff3f3da06c2fc96ccd (diff) | |
| download | llvm-88636854b007affdbe324369b26c9ded66934b22.zip llvm-88636854b007affdbe324369b26c9ded66934b22.tar.gz llvm-88636854b007affdbe324369b26c9ded66934b22.tar.bz2 | |
[RISCV][GISel] Correct registers classes in vector sext/zext.mir tests. NFC
The liveins were always for an LMUL=1 register class even if the
first instruction used a larger regsister class.
One test in zext.mir used the wrong class for the first instruction.
Diffstat (limited to 'lldb/source/Plugins/ScriptInterpreter/Python/PythonReadline.h')
0 files changed, 0 insertions, 0 deletions