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| author | Yingwei Zheng <dtcxzyw2333@gmail.com> | 2023-11-08 00:41:06 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-11-08 00:41:06 +0800 |
| commit | 867ece181afe59aa020d365928169d2ebdc7d74a (patch) | |
| tree | 519611feed2442887bff60ab661b6732c5a1d09d /lldb/source/Plugins/ScriptInterpreter/Python/PythonReadline.h | |
| parent | 2d739f13d49363dd55867e1d8cda80d92d617675 (diff) | |
| download | llvm-867ece181afe59aa020d365928169d2ebdc7d74a.zip llvm-867ece181afe59aa020d365928169d2ebdc7d74a.tar.gz llvm-867ece181afe59aa020d365928169d2ebdc7d74a.tar.bz2 | |
[RISCV] Add processor definition for XiangShan-NanHu (#70294)
This PR adds the processor definition for XiangShan-NanHu, an
open-source high-performance RISC-V processor.
According to the official
[documentation](https://xiangshan-doc.readthedocs.io/zh-cn/latest/arch/),
NanHu core supports
`RV64IMAFDC_zba_zbb_zbc_zbs_zbkb_zbkc_zbkx_zknd_zkne_zknh_zksed_zksh_svinval`.
I found that NanHu also supports `zicbom` and `zicboz`. You can find
them in the [source
code](https://github.com/OpenXiangShan/XiangShan/blob/5931ace35325a644a12f8ea27830a2de7489e7e7/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala#L426-L436).
Features supported by NanHu have been confirmed by @poemonsense.
---------
Co-authored-by: SForeKeeper <zkliu6@gmail.com>
Diffstat (limited to 'lldb/source/Plugins/ScriptInterpreter/Python/PythonReadline.h')
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