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| author | David Sherwood <david.sherwood@arm.com> | 2021-11-16 14:19:18 +0000 |
|---|---|---|
| committer | David Sherwood <david.sherwood@arm.com> | 2021-11-16 16:25:16 +0000 |
| commit | 460745902275c341889bde9daeb41287359e59e3 (patch) | |
| tree | e54681f1756144ddf0c070e0814480e52af25ab0 /lldb/source/Plugins/ScriptInterpreter/Python/PythonReadline.h | |
| parent | 35f798d05d5138613e1392ec1630eec93b0caff9 (diff) | |
| download | llvm-460745902275c341889bde9daeb41287359e59e3.zip llvm-460745902275c341889bde9daeb41287359e59e3.tar.gz llvm-460745902275c341889bde9daeb41287359e59e3.tar.bz2 | |
[AArch64] Fix TypeSize->uint64_t implicit conversion in AArch64ISelLowering::hasAndNot
For now I've just changed the code to only return true from
AArch64ISelLowering::hasAndNot if the vector is fixed-length.
Once we have the right patterns or DAG combines to use bic/bif
we can also enable this for SVE.
Test added here:
CodeGen/AArch64/vselect-constants.ll
Differential Revision: https://reviews.llvm.org/D113994
Diffstat (limited to 'lldb/source/Plugins/ScriptInterpreter/Python/PythonReadline.h')
0 files changed, 0 insertions, 0 deletions