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| author | Craig Topper <craig.topper@sifive.com> | 2022-07-27 17:35:26 -0700 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2022-07-27 17:35:26 -0700 |
| commit | a304d70ee9b8611b60eb1951cbf62cd447520a36 (patch) | |
| tree | 00c9bbf4240c19c502f583e9a9606451ec9c74a7 /lldb/source/Plugins/ScriptInterpreter/Python/PythonReadline.cpp | |
| parent | 8d87f71e548e8241927db90d09379b893cbd5944 (diff) | |
| download | llvm-a304d70ee9b8611b60eb1951cbf62cd447520a36.zip llvm-a304d70ee9b8611b60eb1951cbf62cd447520a36.tar.gz llvm-a304d70ee9b8611b60eb1951cbf62cd447520a36.tar.bz2 | |
[RISCV] Reorder (and/or/xor (shl X, C1), C2) if we can form ANDI/ORI/XORI.
InstCombine and DAGCombine prefer to keep shl before binops.
This patch teaches isel to convert to (shl (and/or/xor X, C1 >> C2), C2)
if (C1 >> C2) is a simm12. The idea was taken from X86's isel code.
There's a special case implemented for a sext_inreg between the
shift and the binop.
Differential Revision: https://reviews.llvm.org/D130610
Diffstat (limited to 'lldb/source/Plugins/ScriptInterpreter/Python/PythonReadline.cpp')
0 files changed, 0 insertions, 0 deletions