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| author | Tim Renouf <tpr.llvm@botech.co.uk> | 2019-03-18 19:35:44 +0000 |
|---|---|---|
| committer | Tim Renouf <tpr.llvm@botech.co.uk> | 2019-03-18 19:35:44 +0000 |
| commit | cfdfba996b081092814d9b0856fcb8b2e12f73e7 (patch) | |
| tree | d748fb4f2debefc9a2f7a358095f9fc0a5f237ec /lldb/source/Plugins/ScriptInterpreter/Python/PythonExceptionState.cpp | |
| parent | 2e94f6e584d9dc95701d54d5dd47fad84d5bf985 (diff) | |
| download | llvm-cfdfba996b081092814d9b0856fcb8b2e12f73e7.zip llvm-cfdfba996b081092814d9b0856fcb8b2e12f73e7.tar.gz llvm-cfdfba996b081092814d9b0856fcb8b2e12f73e7.tar.bz2 | |
[AMDGPU] Asm/disasm clamp modifier on vop3 int arithmetic
Allow the clamp modifier on vop3 int arithmetic instructions in assembly
and disassembly.
This involved adding a clamp operand to the affected instructions in MIR
and MC, and thus having to fix up several places in codegen and MIR
tests.
Differential Revision: https://reviews.llvm.org/D59267
Change-Id: Ic7775105f02a985b668fa658a0cd7837846a534e
llvm-svn: 356399
Diffstat (limited to 'lldb/source/Plugins/ScriptInterpreter/Python/PythonExceptionState.cpp')
0 files changed, 0 insertions, 0 deletions