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| author | Yingwei Zheng <dtcxzyw2333@gmail.com> | 2024-05-22 22:43:10 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-05-22 22:43:10 +0800 |
| commit | c8dc6b59d68635f73d2970b7fc8bc9c6c2684098 (patch) | |
| tree | 049848ba658900273333031ddc176b430b951af8 /lldb/source/Plugins/ScriptInterpreter/Python/Interfaces | |
| parent | 831d1435193e73026e03e006a5b86591f3d202b3 (diff) | |
| download | llvm-c8dc6b59d68635f73d2970b7fc8bc9c6c2684098.zip llvm-c8dc6b59d68635f73d2970b7fc8bc9c6c2684098.tar.gz llvm-c8dc6b59d68635f73d2970b7fc8bc9c6c2684098.tar.bz2 | |
[SDAG] Improve `SimplifyDemandedBits` for mul (#90034)
If the RHS is a constant with X trailing zeros, then the X MSBs of the
LHS are not demanded.
Alive2: https://alive2.llvm.org/ce/z/F5CyJW
Fixes https://github.com/llvm/llvm-project/issues/56645.
Diffstat (limited to 'lldb/source/Plugins/ScriptInterpreter/Python/Interfaces')
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