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| author | Philip Reames <listmail@philipreames.com> | 2020-03-02 13:21:53 -0800 |
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| committer | Philip Reames <listmail@philipreames.com> | 2020-03-02 14:40:25 -0800 |
| commit | 7049cf6496c9aa8e355345a3fbea30861e4d2da8 (patch) | |
| tree | d56252823a37d4e1bebb5d07d5b740e6f76e28fd /lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp | |
| parent | 9897daa6bfcce044473f63e12492ec7748e8eb62 (diff) | |
| download | llvm-7049cf6496c9aa8e355345a3fbea30861e4d2da8.zip llvm-7049cf6496c9aa8e355345a3fbea30861e4d2da8.tar.gz llvm-7049cf6496c9aa8e355345a3fbea30861e4d2da8.tar.bz2 | |
[BranchAlign] Fix bug w/nop padding for SS manipulation
X86 has several instructions which are documented as enabling interrupts exactly one instruction *after* the one which changes the SS segment register. Inserting a nop between these two instructions allows an interrupt to arrive before the execution of the following instruction which changes semantic behaviour.
The list of instructions is documented in "Table 24-3. Format of Interruptibility State" in Volume 3c of the Intel manual. They basically all come down to different ways to write to the SS register.
Differential Revision: https://reviews.llvm.org/D75359
Diffstat (limited to 'lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp')
0 files changed, 0 insertions, 0 deletions