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| author | Jaydeep Patil <jaydeep.patil@imgtec.com> | 2015-06-23 03:37:08 +0000 |
|---|---|---|
| committer | Jaydeep Patil <jaydeep.patil@imgtec.com> | 2015-06-23 03:37:08 +0000 |
| commit | c60c94528cd47100642fba1e0f2e9b8d225d8d67 (patch) | |
| tree | 85ed7a3d7d10a65366009fa871d7d540d6537c3e /lldb/source/Plugins/Process/Linux/NativeProcessLinux.cpp | |
| parent | 49943652f57c92efa02c45f12e23b06a2ac8009b (diff) | |
| download | llvm-c60c94528cd47100642fba1e0f2e9b8d225d8d67.zip llvm-c60c94528cd47100642fba1e0f2e9b8d225d8d67.tar.gz llvm-c60c94528cd47100642fba1e0f2e9b8d225d8d67.tar.bz2 | |
[LLDB][MIPS] MIPS32 branch emulation and single-stepping
SUMMARY:
This patch implements
1. Emulation of MIPS32 branch instructions
2. Enable single-stepping for MIPS32 instructions
3. Correction in emulation of MIPS64 branch instructions with delay slot
4. Adjust breakpoint address when breakpoint is hit in a forbidden slot of compact branch instruction
Reviewers: clayborg
Subscribers: mohit.bhakkad, sagar, bhushan, lldb-commits, emaste, nitesh.jain
Differential Revision: http://reviews.llvm.org/D10596
llvm-svn: 240373
Diffstat (limited to 'lldb/source/Plugins/Process/Linux/NativeProcessLinux.cpp')
| -rw-r--r-- | lldb/source/Plugins/Process/Linux/NativeProcessLinux.cpp | 14 |
1 files changed, 8 insertions, 6 deletions
diff --git a/lldb/source/Plugins/Process/Linux/NativeProcessLinux.cpp b/lldb/source/Plugins/Process/Linux/NativeProcessLinux.cpp index be4b319..ffafbac 100644 --- a/lldb/source/Plugins/Process/Linux/NativeProcessLinux.cpp +++ b/lldb/source/Plugins/Process/Linux/NativeProcessLinux.cpp @@ -2018,7 +2018,7 @@ NativeProcessLinux::MonitorSIGTRAP(const siginfo_t *info, lldb::pid_t pid) { // If a watchpoint was hit, report it uint32_t wp_index; - Error error = thread_sp->GetRegisterContext()->GetWatchpointHitIndex(wp_index, NULL); + Error error = thread_sp->GetRegisterContext()->GetWatchpointHitIndex(wp_index, LLDB_INVALID_ADDRESS); if (error.Fail() && log) log->Printf("NativeProcessLinux::%s() " "received error while checking for watchpoint hits, " @@ -2442,7 +2442,9 @@ NativeProcessLinux::SetupSoftwareSingleStepping(NativeThreadProtocolSP thread_sp } } else if (m_arch.GetMachine() == llvm::Triple::mips64 - || m_arch.GetMachine() == llvm::Triple::mips64el) + || m_arch.GetMachine() == llvm::Triple::mips64el + || m_arch.GetMachine() == llvm::Triple::mips + || m_arch.GetMachine() == llvm::Triple::mipsel) error = SetSoftwareBreakpoint(next_pc, 4); else { @@ -2462,7 +2464,8 @@ bool NativeProcessLinux::SupportHardwareSingleStepping() const { if (m_arch.GetMachine() == llvm::Triple::arm - || m_arch.GetMachine() == llvm::Triple::mips64 || m_arch.GetMachine() == llvm::Triple::mips64el) + || m_arch.GetMachine() == llvm::Triple::mips64 || m_arch.GetMachine() == llvm::Triple::mips64el + || m_arch.GetMachine() == llvm::Triple::mips || m_arch.GetMachine() == llvm::Triple::mipsel) return false; return true; } @@ -3028,7 +3031,6 @@ NativeProcessLinux::GetSoftwareBreakpointPCOffset (NativeRegisterContextSP conte // set per architecture. Need ARM, MIPS support here. static const uint8_t g_aarch64_opcode[] = { 0x00, 0x00, 0x20, 0xd4 }; static const uint8_t g_i386_opcode [] = { 0xCC }; - static const uint8_t g_mips64_opcode[] = { 0x00, 0x00, 0x00, 0x0d }; switch (m_arch.GetMachine ()) { @@ -3049,7 +3051,7 @@ NativeProcessLinux::GetSoftwareBreakpointPCOffset (NativeRegisterContextSP conte case llvm::Triple::mips64el: case llvm::Triple::mips: case llvm::Triple::mipsel: - actual_opcode_size = static_cast<uint32_t> (sizeof(g_mips64_opcode)); + actual_opcode_size = 0; return Error (); default: @@ -3553,7 +3555,7 @@ NativeProcessLinux::FixupBreakpointPCAsNeeded (NativeThreadProtocolSP &thread_sp } // First try probing for a breakpoint at a software breakpoint location: PC - breakpoint size. - const lldb::addr_t initial_pc_addr = context_sp->GetPC (); + const lldb::addr_t initial_pc_addr = context_sp->GetPCfromBreakpointLocation (); lldb::addr_t breakpoint_addr = initial_pc_addr; if (breakpoint_size > 0) { |