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| author | Jaydeep Patil <jaydeep.patil@imgtec.com> | 2015-09-22 06:36:56 +0000 |
|---|---|---|
| committer | Jaydeep Patil <jaydeep.patil@imgtec.com> | 2015-09-22 06:36:56 +0000 |
| commit | 44d07fcc7c610730950e7e914e9e3bfb6736e65e (patch) | |
| tree | 6f3879ca2b2d899443cec6ed9f9842cef9bf0f9d /lldb/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp | |
| parent | 132c2c4bc7fd53b85b68b2d05033e05aa2585587 (diff) | |
| download | llvm-44d07fcc7c610730950e7e914e9e3bfb6736e65e.zip llvm-44d07fcc7c610730950e7e914e9e3bfb6736e65e.tar.gz llvm-44d07fcc7c610730950e7e914e9e3bfb6736e65e.tar.bz2 | |
[LLDB][MIPS] microMIPS breakpoints, disassembly and compressed addresses
SUMMARY:
This patch detects microMIPS symbols, sets breakpoints using un-compressed address and
display disassembly in mixed mode for microMIPS applications (running on bare-iron targets).
Reviewers: clayborg
Subscribers: nitesh.jain, mohit.bhakkad, sagar, bhushan and lldb-commits
Differential Revision: http://reviews.llvm.org/D12079
llvm-svn: 248248
Diffstat (limited to 'lldb/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp')
| -rw-r--r-- | lldb/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp | 27 |
1 files changed, 22 insertions, 5 deletions
diff --git a/lldb/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp b/lldb/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp index d527bdc6..6626c92 100644 --- a/lldb/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp +++ b/lldb/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp @@ -736,10 +736,6 @@ DisassemblerLLVMC::DisassemblerLLVMC (const ArchSpec &arch, const char *flavor_s features_str += "+dsp,"; if (arch_flags & ArchSpec::eMIPSAse_dspr2) features_str += "+dspr2,"; - if (arch_flags & ArchSpec::eMIPSAse_mips16) - features_str += "+mips16,"; - if (arch_flags & ArchSpec::eMIPSAse_micromips) - features_str += "+micromips,"; } m_disasm_ap.reset (new LLVMCDisassembler(triple_str, cpu, features_str.c_str(), flavor, *this)); @@ -750,8 +746,10 @@ DisassemblerLLVMC::DisassemblerLLVMC (const ArchSpec &arch, const char *flavor_s m_disasm_ap.reset(); } + llvm::Triple::ArchType llvm_arch = triple.getArch(); + // For arm CPUs that can execute arm or thumb instructions, also create a thumb instruction disassembler. - if (triple.getArch() == llvm::Triple::arm) + if (llvm_arch == llvm::Triple::arm) { std::string thumb_triple(thumb_arch.GetTriple().getTriple()); m_alternate_disasm_ap.reset(new LLVMCDisassembler(thumb_triple.c_str(), "", "", flavor, *this)); @@ -761,6 +759,25 @@ DisassemblerLLVMC::DisassemblerLLVMC (const ArchSpec &arch, const char *flavor_s m_alternate_disasm_ap.reset(); } } + else if (llvm_arch == llvm::Triple::mips + || llvm_arch == llvm::Triple::mipsel + || llvm_arch == llvm::Triple::mips64 + || llvm_arch == llvm::Triple::mips64el) + { + /* Create alternate disassembler for MIPS16 and microMIPS */ + uint32_t arch_flags = arch.GetFlags (); + if (arch_flags & ArchSpec::eMIPSAse_mips16) + features_str += "+mips16,"; + else if (arch_flags & ArchSpec::eMIPSAse_micromips) + features_str += "+micromips,"; + + m_alternate_disasm_ap.reset(new LLVMCDisassembler (triple_str, cpu, features_str.c_str(), flavor, *this)); + if (!m_alternate_disasm_ap->IsValid()) + { + m_disasm_ap.reset(); + m_alternate_disasm_ap.reset(); + } + } } DisassemblerLLVMC::~DisassemblerLLVMC() |