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| author | Emmmer <yjhdandan@163.com> | 2022-08-10 21:36:20 +0800 |
|---|---|---|
| committer | Emmmer <yjhdandan@163.com> | 2022-08-11 14:24:06 +0800 |
| commit | 7bece0f03bf6cbf7f98812b7cff0e789709c9982 (patch) | |
| tree | 41cdafb060468c94a21a21f6c2925949ecdd96cf /lldb/source/Host/common/NativeProcessProtocol.cpp | |
| parent | 9381de09526104fd08d0eef03032d6fbe491b9d1 (diff) | |
| download | llvm-7bece0f03bf6cbf7f98812b7cff0e789709c9982.zip llvm-7bece0f03bf6cbf7f98812b7cff0e789709c9982.tar.gz llvm-7bece0f03bf6cbf7f98812b7cff0e789709c9982.tar.bz2 | |
[LLDB][RISCV] Add riscv register definition and read/write
This patch is based on the minimal extract of D128250.
What is implemented:
- Use the same register layout as Linux kernel and mock read/write for `x0` register (the always zero register).
- Refactor some duplicate code, and delete unused register definitions.
Reviewed By: DavidSpickett
Differential Revision: https://reviews.llvm.org/D130342
Diffstat (limited to 'lldb/source/Host/common/NativeProcessProtocol.cpp')
0 files changed, 0 insertions, 0 deletions