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| author | Aart Bik <ajcbik@google.com> | 2023-03-14 21:43:20 -0700 |
|---|---|---|
| committer | Aart Bik <ajcbik@google.com> | 2023-03-17 09:22:15 -0700 |
| commit | 4e4af1338da5bdbf10e113c0462d7eb7222b5d97 (patch) | |
| tree | 6695fb0bbb3f33f34df1ab79ea2da46db3493657 /lldb/source/Commands/CommandObjectWatchpoint.cpp | |
| parent | 9aa01c4e8917569a7557fe05b278fc0892c9b56a (diff) | |
| download | llvm-4e4af1338da5bdbf10e113c0462d7eb7222b5d97.zip llvm-4e4af1338da5bdbf10e113c0462d7eb7222b5d97.tar.gz llvm-4e4af1338da5bdbf10e113c0462d7eb7222b5d97.tar.bz2 | |
[mlir][gpu][nvvm] fixed bug with literal for inline asm for mma instruction
The 'mma.sp.sync.aligned' family of instructions expects
the sparsity selector as a direct literal (0x0 or 0x1).
The current MLIR inline asm passed this as a value in
register, which broke the downstream assemblers
This is a small step towards supporting 2:4 sparsity on
NVidia GPUs in the sparse compiler of MLIR.
Reviewed By: ThomasRaoux, guraypp
Differential Revision: https://reviews.llvm.org/D146110
Diffstat (limited to 'lldb/source/Commands/CommandObjectWatchpoint.cpp')
0 files changed, 0 insertions, 0 deletions