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| author | Min-Yih Hsu <min.hsu@sifive.com> | 2025-09-04 12:35:35 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-09-04 19:35:35 +0000 |
| commit | b45582fe9842c18b1023d60077b4241d4c7380d4 (patch) | |
| tree | c85daca040e7eb23d0623fc6ea5cf04e64cfaeee /lldb/source/Commands/CommandObjectThread.cpp | |
| parent | fffd6da2b4f05e4b7987eb4360f06a56d9313c09 (diff) | |
| download | llvm-b45582fe9842c18b1023d60077b4241d4c7380d4.zip llvm-b45582fe9842c18b1023d60077b4241d4c7380d4.tar.gz llvm-b45582fe9842c18b1023d60077b4241d4c7380d4.tar.bz2 | |
[RISCV][VLOPT] Support segmented store instructions (#155467)
Add RISCVVLOptimizer supported for unit-stride, strided, and indexed
strided segmented stores. The biggest change was adding the capability
to look through INSERT_SUBREG, which was used for composing segmented
register class values.
Fix #149350
Diffstat (limited to 'lldb/source/Commands/CommandObjectThread.cpp')
0 files changed, 0 insertions, 0 deletions