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| author | Carl Ritson <carl.ritson@amd.com> | 2021-06-24 09:59:55 +0900 |
|---|---|---|
| committer | Carl Ritson <carl.ritson@amd.com> | 2021-06-24 12:41:22 +0900 |
| commit | 98f48723f2ca286d6f12bb0c4dc7830a55e85637 (patch) | |
| tree | 60be8084cce59d20ce2443c8426ee84f7c41c73e /lldb/source/Commands/CommandObjectThread.cpp | |
| parent | 6b0f98d442e0cf2b6e3a20ba518abb5549aa4999 (diff) | |
| download | llvm-98f48723f2ca286d6f12bb0c4dc7830a55e85637.zip llvm-98f48723f2ca286d6f12bb0c4dc7830a55e85637.tar.gz llvm-98f48723f2ca286d6f12bb0c4dc7830a55e85637.tar.bz2 | |
[AMDGPU] Add 224-bit vector types and link 192-bit types to MVTs
Add SReg_224, VReg_224, AReg_224, etc.
Link 224-bit types with v7i32/v7f32.
Link existing 192-bit types to newly added v3i64/v3f64/v6i32/v6f32.
Reviewed By: rampitec
Differential Revision: https://reviews.llvm.org/D104622
Diffstat (limited to 'lldb/source/Commands/CommandObjectThread.cpp')
0 files changed, 0 insertions, 0 deletions