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| author | Craig Topper <craig.topper@sifive.com> | 2022-07-14 16:07:03 -0700 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2022-07-14 16:10:14 -0700 |
| commit | dcfc1fd26f6c2e6ecb1f8f9ae1b77d7b5c30c434 (patch) | |
| tree | e290d6bd5f57d878dd1aca9e1f9caac6179faa1f /lldb/source/Commands/CommandObjectProcess.cpp | |
| parent | 450f0bd17b749850c50ce925cb987a5329a656f0 (diff) | |
| download | llvm-dcfc1fd26f6c2e6ecb1f8f9ae1b77d7b5c30c434.zip llvm-dcfc1fd26f6c2e6ecb1f8f9ae1b77d7b5c30c434.tar.gz llvm-dcfc1fd26f6c2e6ecb1f8f9ae1b77d7b5c30c434.tar.bz2 | |
[SelectionDAG][RISCV][AMDGPU][ARM] Improve SimplifyDemandedBits for SHL with variable shift amount.
If we have a variable shift amount and the demanded mask has leading
zeros, we can propagate those leading zeros to not demand those bits
from operand 0. This can allow zero_extend/sign_extend to become
any_extend. This pattern can occur due to C integer promotion rules.
This transform is already done by InstCombineSimplifyDemanded.cpp where
sign_extend can be turned into zero_extend for example.
Reviewed By: spatel, foad
Differential Revision: https://reviews.llvm.org/D121833
Diffstat (limited to 'lldb/source/Commands/CommandObjectProcess.cpp')
0 files changed, 0 insertions, 0 deletions