[RISCV] Factor out common SiFive7 scheduling model into an abstraction layer (#144442)

In preparation for sifive-x390's scheduling model, which shares quite a
lot with the existing SiFive7 scheduling model, this patch factors out
some of the components that will share between them. Notably:

- Processor resource definitions (i.e. pipes) are factored out into a
multiclass, `SiFive7ProcResources`. Similarly, WriteRes entries and
bypass entries (i.e. ReadAdvance) are also factored out into their own
multiclass: `SiFive7WriteResBase` and `SiFive7ReadAdvance`,
respectively.
- The aforementioned three components, `SiFive7ProcResources`,
`SiFive7WriteResBase`, and `SiFive7ReadAdvance` are encapsulated into a
bigger multiclass, `SiFive7SchedResources`, which configures these
components with parameters passed from the template arguments. An
example configure value would be the VLEN.
- SiFive7's SchedMachineModel carries not only standard fields like
issue width, but also the concrete config values corresponding to the
processor. For instance, the existing SiFive7 models has VLEN=512, while
X390 has VLEN=1024.
- In the final phase, we "bind" SchedMachineModel from each processor to
a SiFive7SchedResources that is instantiated from that
SchedMachineModel's config values.

Co-authored-by: Michael Maitland <michaeltmaitland@gmail.com>

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