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| author | David Green <david.green@arm.com> | 2022-05-19 13:54:35 +0100 |
|---|---|---|
| committer | David Green <david.green@arm.com> | 2022-05-19 13:54:35 +0100 |
| commit | 602f81ec336330f97e22442b98035c6f007cac6d (patch) | |
| tree | 67267ba18d378d77908c528378f82d9115dd7df2 /lldb/source/Commands/CommandObjectMemory.cpp | |
| parent | 017c98276b07a0abd1204ff34ee2b8f761099fac (diff) | |
| download | llvm-602f81ec336330f97e22442b98035c6f007cac6d.zip llvm-602f81ec336330f97e22442b98035c6f007cac6d.tar.gz llvm-602f81ec336330f97e22442b98035c6f007cac6d.tar.bz2 | |
[AArch64] Fix zero element TBL indices
A TBL instruction will fill out-of-range values with 0's, something used
in D121139 to turn tbl2 with a zero input into tbl1s. This works OK for
v16i8, but for v8i8 the input is still treated as a v16i8, so
out-of-range values (like a lane index of 8) would end up loading values
from the top half of the input register. Clean this up by detecting the
out of range values and making sure they really use out of range values.
There is a fix for swapped indices of 64bit input vectors too, which
could be incorrectly adjusted if the zerovector was the first operand.
Fixes #55545
Differential Revision: https://reviews.llvm.org/D125865
Diffstat (limited to 'lldb/source/Commands/CommandObjectMemory.cpp')
0 files changed, 0 insertions, 0 deletions