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| author | Craig Topper <craig.topper@intel.com> | 2019-10-28 11:10:49 -0700 |
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| committer | Craig Topper <craig.topper@intel.com> | 2019-10-28 11:27:01 -0700 |
| commit | 3da269a2489f156462fca74311842d761151393f (patch) | |
| tree | 9dd51543e74026276ff668170942518e38ff70cc /lldb/scripts/Python/use_lldb_suite.py | |
| parent | 8aa0a785c423ebea84876b71f7b735bee96a0292 (diff) | |
| download | llvm-3da269a2489f156462fca74311842d761151393f.zip llvm-3da269a2489f156462fca74311842d761151393f.tar.gz llvm-3da269a2489f156462fca74311842d761151393f.tar.bz2 | |
[X86] Add a DAG combine to turn (and (bitcast (vXi1 (concat_vectors (vYi1 setcc), undef,))), C) into (bitcast (vXi1 (concat_vectors (vYi1 setcc), zero,)))
The legalization of v2i1->i2 or v4i1->i4 bitcasts followed by a setcc can create an and after the bitcast. If we're lucky enough that the input to the bitcast is a concat_vectors where the first operand is a setcc that can natively 0 all the upper bits of ak-register, then we should replace the other operands of the concat_vectors with zero in order to remove the AND.
With the AND removed we might be able to use a kortest on the result.
Differential Revision: https://reviews.llvm.org/D69205
Diffstat (limited to 'lldb/scripts/Python/use_lldb_suite.py')
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