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authorLuke Lau <luke@igalia.com>2024-09-12 08:41:50 +0800
committerGitHub <noreply@github.com>2024-09-12 08:41:50 +0800
commit480f07ff6c7ac2d928b6f1862698dbd51069735c (patch)
tree684fbcb297b02c178b923a9579799e1c862a216e /lldb/packages/Python/lldbsuite/test
parent3cd01371e007b2a8fe32e5d8ce1154057e5e1c2e (diff)
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[RISCV] Add fixed length vector patterns for vfwmaccbf16.vv (#108204)
This adds VL patterns for vfwmaccbf16.vv so that we can handle fixed length vectors. It does this by teaching combineOp_VLToVWOp_VL to emit RISCVISD::VFWMADD_VL for bf16. The change in getOrCreateExtendedOp is needed because getNarrowType is based off of the bitwidth so returns f16. We need to explicitly check for bf16. Note that the .vf patterns don't work yet, since the build_vector splat gets lowered to a (vmv_v_x_vl (fmv_x_anyexth x)) instead of a vfmv.v.f, which SplatFP doesn't pick up, see #106637.
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