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| author | Craig Topper <craig.topper@sifive.com> | 2022-08-11 12:59:04 -0700 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2022-08-11 14:24:09 -0700 |
| commit | 2c79801a0e572e1f25a249596d963ad178cfcda5 (patch) | |
| tree | 075051ed5347535e3a00e7144ffcb795093e5b8e /lldb/packages/Python/lldbsuite/test | |
| parent | 2608f553b8fd02bfd5a81d9e45406cee0c2dfe26 (diff) | |
| download | llvm-2c79801a0e572e1f25a249596d963ad178cfcda5.zip llvm-2c79801a0e572e1f25a249596d963ad178cfcda5.tar.gz llvm-2c79801a0e572e1f25a249596d963ad178cfcda5.tar.bz2 | |
[RISCV] Add more ineg+setcc isel patterns to avoid creating neg+xori+slti(u).
Including patterns to select addiw if only the lower 32 bits are used.
I'm not excited about adding this many patterns. I'm looking at whether
we can create the xori during lowering and move the ineg patterns to
DAGCombiner.
Diffstat (limited to 'lldb/packages/Python/lldbsuite/test')
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