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| author | Craig Topper <craig.topper@sifive.com> | 2021-02-21 11:13:34 -0800 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2021-02-21 11:13:36 -0800 |
| commit | 1a6c1ac6862a10c2484ea2880ea9b67ad8b9c144 (patch) | |
| tree | 95bc5f5a533f207925504b5cc305ea5f0c1bc35f /lldb/packages/Python/lldbsuite/test | |
| parent | bae04a3e2d69d474e47ce1a23109efa0036e8cf7 (diff) | |
| download | llvm-1a6c1ac6862a10c2484ea2880ea9b67ad8b9c144.zip llvm-1a6c1ac6862a10c2484ea2880ea9b67ad8b9c144.tar.gz llvm-1a6c1ac6862a10c2484ea2880ea9b67ad8b9c144.tar.bz2 | |
[SelectionDAG][RISCV] Teach ComputeNumSignBits to handle SREM.
This also removes a pattern from RISCV that is no longer needed
since the sexti32 on the LHS of the srem in the pattern implies
the result is sign extended so the sign_extend_inreg should be
removed in DAG combine now.
Reviewed By: luismarques, RKSimon
Differential Revision: https://reviews.llvm.org/D97133
Diffstat (limited to 'lldb/packages/Python/lldbsuite/test')
0 files changed, 0 insertions, 0 deletions