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| author | Carl Ritson <carl.ritson@amd.com> | 2025-10-13 13:37:26 +0900 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-10-13 13:37:26 +0900 |
| commit | 1d0a85a78b7ec7b994b280d30ca125fe58dbbd84 (patch) | |
| tree | 380ff14c1b7b50a23f130a9370f3a1cd8f756039 /lldb/packages/Python/lldbsuite/test/lldbutil.py | |
| parent | 36f26d435087fda290e6d08acda59201a91f1d15 (diff) | |
| download | llvm-1d0a85a78b7ec7b994b280d30ca125fe58dbbd84.zip llvm-1d0a85a78b7ec7b994b280d30ca125fe58dbbd84.tar.gz llvm-1d0a85a78b7ec7b994b280d30ca125fe58dbbd84.tar.bz2 | |
[AMDGPU][True16][CodeGen] Add patterns to reduce intermediates (#162047)
Add patterns which reduce or operations to register sequences when
combining i16 values to i32. This removes many intermediate VGPRs and
reduces registers pressure.
Diffstat (limited to 'lldb/packages/Python/lldbsuite/test/lldbutil.py')
0 files changed, 0 insertions, 0 deletions