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| author | David Spickett <david.spickett@linaro.org> | 2025-03-10 10:10:19 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-03-10 10:10:19 +0000 |
| commit | fe544d404d841ef44aebf4fc36948fd1e1d89685 (patch) | |
| tree | f8bde68f3445264411d10728da2e224741ae1a0c /lldb/packages/Python/lldbsuite/test/lldbtest.py | |
| parent | 2aca7c231a573191fbba83ba202bcc245cab6501 (diff) | |
| download | llvm-fe544d404d841ef44aebf4fc36948fd1e1d89685.zip llvm-fe544d404d841ef44aebf4fc36948fd1e1d89685.tar.gz llvm-fe544d404d841ef44aebf4fc36948fd1e1d89685.tar.bz2 | |
[lldb] Add more ARM checks in TestLldbGdbServer.py (#130277)
When https://github.com/llvm/llvm-project/pull/130034 enabled RISC-V
here I noticed that these should run for ARM as well.
ARM only has 4 argument registers, which matches Arm's ABI for it:
https://github.com/ARM-software/abi-aa/blob/main/aapcs32/aapcs32.rst#core-registers
The ABI defines a link register LR, and I assume that's what becomes
'ra' in LLDB.
Tested on ARM and AArch64 Linux.
Diffstat (limited to 'lldb/packages/Python/lldbsuite/test/lldbtest.py')
| -rw-r--r-- | lldb/packages/Python/lldbsuite/test/lldbtest.py | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/lldb/packages/Python/lldbsuite/test/lldbtest.py b/lldb/packages/Python/lldbsuite/test/lldbtest.py index 7d0e6e9..590024e 100644 --- a/lldb/packages/Python/lldbsuite/test/lldbtest.py +++ b/lldb/packages/Python/lldbsuite/test/lldbtest.py @@ -1344,6 +1344,13 @@ class Base(unittest.TestCase): arch = self.getArchitecture().lower() return arch in ["aarch64", "arm64", "arm64e"] + def isARM(self): + """Returns true if the architecture is ARM, meaning 32-bit ARM. Which could + be M profile, A profile Armv7-a, or the AArch32 mode of Armv8-a.""" + return not self.isAArch64() and ( + self.getArchitecture().lower().startswith("arm") + ) + def isAArch64SVE(self): return self.isAArch64() and "sve" in self.getCPUInfo() |