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| author | Craig Topper <craig.topper@intel.com> | 2018-03-20 03:55:17 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-03-20 03:55:17 +0000 |
| commit | 4778fa7e8aea5e4df700cb88651b9fd2e6a7e73b (patch) | |
| tree | a597d582ac8f1d70e045fe5e38ad88f8e1b1c255 /lldb/packages/Python/lldbsuite/test/lldbpexpect.py | |
| parent | 4cca7d229ed2a4a205ee5e5963e924af1af391f7 (diff) | |
| download | llvm-4778fa7e8aea5e4df700cb88651b9fd2e6a7e73b.zip llvm-4778fa7e8aea5e4df700cb88651b9fd2e6a7e73b.tar.gz llvm-4778fa7e8aea5e4df700cb88651b9fd2e6a7e73b.tar.bz2 | |
[X86] Fix the SchedRW for memory forms of CMP and TEST.
They were incorrectly marked as RMW operations. Some of the CMP instrucions worked, but the ones that use a similar encoding as RMW form of ADD ended up marked as RMW.
TEST used the same tablegen class as some of the CMPs.
llvm-svn: 327947
Diffstat (limited to 'lldb/packages/Python/lldbsuite/test/lldbpexpect.py')
0 files changed, 0 insertions, 0 deletions