[RISCV] Remove post-decoding instruction adjustments (#156360)

Some instructions implicitly define/use X2 (SP) register, but instead of
being present in the Defs/Uses lists, it is sometimes modeled as an
explicit operand with SP register class.
Since the operand is not encoded into the instruction, it cannot be
disassembled, and we have `RISCVDisassembler::addSPOperands()` that
addresses the issue by mutating the (incompletely) decoded instruction.

This change makes the operand decodable by adding `bits<0>` field for
that operand to relevant instruction encodings and removes
`RISCVDisassembler::addSPOperands()`.

0 files changed, 0 insertions, 0 deletions