[TableGen][DecoderEmitter] Resolve a FIXME in emitDecoder (#154649)

As the FIXME says, we might generate the wrong code to decode an
instruction if it had an operand with no encoding bits. An example is
M68k's `MOV16ds` that is defined as follows:

```
dag OutOperandList = (outs MxDRD16:$dst);
dag InOperandList = (ins SRC:$src);
list<Register> Uses = [SR];
string AsmString = "move.w\t$src, $dst"
dag Inst = (descend { 0, 1, 0, 0, 0, 0, 0, 0, 1, 1 },
            (descend { 0, 0, 0 }, (operand "$dst", 3)));
```

The `$src` operand is not encoded, but what we see in the decoder is:
```C++
    tmp = fieldFromInstruction(insn, 0, 3);
    if (!Check(S, DecodeDR16RegisterClass(MI, tmp, Address, Decoder)))
    { return MCDisassembler::Fail; }
    if (!Check(S, DecodeSRCRegisterClass(MI, insn, Address, Decoder)))
    { return MCDisassembler::Fail; }
    return S;
```

This calls DecodeSRCRegisterClass passing it `insn` instead of the value
of a field that doesn't exist. DecodeSRCRegisterClass has an
unconditional llvm_unreachable inside it.

New decoder looks like:
```C++
    tmp = fieldFromInstruction(insn, 0, 3);
    if (!Check(S, DecodeDR16RegisterClass(MI, tmp, Address, Decoder)))
    { return MCDisassembler::Fail; }
    return S;
```

We're still not disassembling this instruction right, but at least we no
longer have to provide a weird operand decoder method that accepts
instruction bits instead of operand bits.

See #154477 for the origins of the FIXME.

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