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| author | Craig Topper <craig.topper@sifive.com> | 2022-03-23 09:28:46 -0700 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2022-03-23 09:52:07 -0700 |
| commit | cac9773dccd95cd442d2852b7ced0a8a311504f6 (patch) | |
| tree | 8e0cf7286a79015b97ae33674f6d4b4d41edd4c9 /lldb/packages/Python/lldbsuite/test/gdbclientutils.py | |
| parent | b38e78cc445c0b6e119e8b3b7e42371caab14a05 (diff) | |
| download | llvm-cac9773dccd95cd442d2852b7ced0a8a311504f6.zip llvm-cac9773dccd95cd442d2852b7ced0a8a311504f6.tar.gz llvm-cac9773dccd95cd442d2852b7ced0a8a311504f6.tar.bz2 | |
[SelectionDAG] Don't create entries in ValueMap in ComputePHILiveOutRegInfo
Instead of using operator[], use DenseMap::find to prevent default
constructing an entry if it isn't already in the map.
Also simplify a condition to check for 0 instead of a virtual register.
I'm pretty sure we can only get 0 or a virtual register out of the value
map.
Diffstat (limited to 'lldb/packages/Python/lldbsuite/test/gdbclientutils.py')
0 files changed, 0 insertions, 0 deletions