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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2025-10-01 00:18:51 +0900 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-10-01 00:18:51 +0900 |
| commit | 981122696701d3c3897af267afd73bbefa61c3d4 (patch) | |
| tree | 16272d3733773e950b35f69645a7f22dbbb971e7 /lldb/packages/Python/lldbsuite/test/gdbclientutils.py | |
| parent | 58b4951726aa1cf92ca08f9b87f5ea7d28700e75 (diff) | |
| download | llvm-981122696701d3c3897af267afd73bbefa61c3d4.zip llvm-981122696701d3c3897af267afd73bbefa61c3d4.tar.gz llvm-981122696701d3c3897af267afd73bbefa61c3d4.tar.bz2 | |
PeepholeOpt: Try to constrain uses to support subregister (#161338)
This allows removing a special case hack in ARM. ARM's implementation
of getExtractSubregLikeInputs has the strange property that it reports
a register with a class that does not support the reported subregister
index. We can however reconstrain the register to support this usage.
This is an alternative to #159600. I've included the test, but
the output is different. In this case version the VMOVSR is
replaced with an ordinary subregister extract copy.
Diffstat (limited to 'lldb/packages/Python/lldbsuite/test/gdbclientutils.py')
0 files changed, 0 insertions, 0 deletions