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authorSander de Smalen <sander.desmalen@arm.com>2022-07-06 16:14:51 +0000
committerSander de Smalen <sander.desmalen@arm.com>2022-07-07 07:39:27 +0000
commit6106a767b723134a944ac4f2152c92b140d7a5f4 (patch)
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[AArch64][SME] Update load/store intrinsics to take predicate corresponding to element size.
Instead of using <vscale x 16 x i1> for all the loads/stores, we now use the appropriate predicate type according to the element size, e.g. ld1b uses <vscale x 16 x i1> ld1w uses <vscale x 4 x i1> ld1q uses <vscale x 1 x i1> Reviewed By: kmclaughlin Differential Revision: https://reviews.llvm.org/D129083
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