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| author | Craig Topper <craig.topper@sifive.com> | 2025-07-28 21:35:09 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-07-28 21:35:09 -0700 |
| commit | dbcbdc4da0a9f4627562c305492b4464afe5b467 (patch) | |
| tree | 00e114a7662888e69781b1f5a78e76e5528704c8 /lldb/packages/Python/lldbsuite/test/configuration.py | |
| parent | 19ba224fb8a925d095d84836bc9896bf564dfd99 (diff) | |
| download | llvm-dbcbdc4da0a9f4627562c305492b4464afe5b467.zip llvm-dbcbdc4da0a9f4627562c305492b4464afe5b467.tar.gz llvm-dbcbdc4da0a9f4627562c305492b4464afe5b467.tar.bz2 | |
[RISCV] Add IsSignExtendingOpW to P-ext CLS, CLSW, and ABSW instructions. (#151037)
This matches other W instructions. CLS is included since it can only
return 0-64 which has bits [63:31] as zero. This is similar to CLZ.
This doesn't do anything yet since we don't have CodeGen support for P.
Diffstat (limited to 'lldb/packages/Python/lldbsuite/test/configuration.py')
0 files changed, 0 insertions, 0 deletions