diff options
| author | David Green <david.green@arm.com> | 2021-03-02 19:01:14 +0000 |
|---|---|---|
| committer | David Green <david.green@arm.com> | 2021-03-02 19:01:14 +0000 |
| commit | 438c98515c23a111992d332e316824d0a17f2ea4 (patch) | |
| tree | b4893c55a98b8a7612df8783915f5e2541dd1443 /libcxx/src/filesystem/operations.cpp | |
| parent | 52bbbf4d4459239e0f461bc302ada89e2c5d07fc (diff) | |
| download | llvm-438c98515c23a111992d332e316824d0a17f2ea4.zip llvm-438c98515c23a111992d332e316824d0a17f2ea4.tar.gz llvm-438c98515c23a111992d332e316824d0a17f2ea4.tar.bz2 | |
[ARM] Use 0, not ZR during ISel for CSINC/INV/NEG
Instead of converting the 0 into a ZR reg during lowering, do that with
tablegen by matching the zero immediate. This when combined with other
optimizations is more likely to use ZR and helps keep the DAG more
easily optimizable. It should not otherwise effect code generation.
Diffstat (limited to 'libcxx/src/filesystem/operations.cpp')
0 files changed, 0 insertions, 0 deletions