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authorCraig Topper <craig.topper@sifive.com>2021-06-04 08:57:07 -0700
committerCraig Topper <craig.topper@sifive.com>2021-06-04 09:17:46 -0700
commitc653711fd3a9ac8399a435f02054ef42cddc4db7 (patch)
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parentb109172d993edacd9853a8bbb8128a94da014399 (diff)
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[RISCV] Teach vsetvli insertion pass that operations on masks don't care about SEW/LMUL.
All that really matters is that the VLMAX of the preceding instructions is the same as the VLMAX required by the mask operation. Also update the vmsge(u) handling to use the SEW/LMUL we use for other mask register operations. We were matching it to the compare before. Some cases will be improve if we fix masked compares to use tail agnostic policy. I think they ignore the tail policy anyway. Reviewed By: frasercrmck Differential Revision: https://reviews.llvm.org/D103299
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