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| author | Craig Topper <craig.topper@sifive.com> | 2021-06-24 15:53:47 -0700 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2021-06-24 18:06:36 -0700 |
| commit | f225367305c82ce391bb470f735b19e924ff7372 (patch) | |
| tree | 8949c2a9e112a7705aa2f7b21a0e2e19109a1fd4 /flang/lib/Frontend/CompilerInvocation.cpp | |
| parent | e8cded57fbf7b2b81aefd569b95f38ae97948ef0 (diff) | |
| download | llvm-f225367305c82ce391bb470f735b19e924ff7372.zip llvm-f225367305c82ce391bb470f735b19e924ff7372.tar.gz llvm-f225367305c82ce391bb470f735b19e924ff7372.tar.bz2 | |
[RISCV] Add vget/vset intrinsics for inserting and extracting between different lmuls.
These allow getting a whole register from a larger lmul. Or
inserting a whole register into a larger lmul register. Fractional
lmuls are not supported as they would require a vslide.
Based on this update to the intrinsic doc
https://github.com/riscv/rvv-intrinsic-doc/pull/99
Reviewed By: HsiangKai
Differential Revision: https://reviews.llvm.org/D104822
Diffstat (limited to 'flang/lib/Frontend/CompilerInvocation.cpp')
0 files changed, 0 insertions, 0 deletions