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| author | Carl Ritson <carl.ritson@amd.com> | 2023-11-13 12:21:18 +0900 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-11-13 12:21:18 +0900 |
| commit | edc38a6cbd12a7cfa5d3c4de9767333c442ef2eb (patch) | |
| tree | 28c940ebba304b4068c7ef912d054a3e812b7a99 /flang/lib/Frontend/CompilerInvocation.cpp | |
| parent | 6428bdd05d57276a9d1eda96963911695d4d7d9a (diff) | |
| download | llvm-edc38a6cbd12a7cfa5d3c4de9767333c442ef2eb.zip llvm-edc38a6cbd12a7cfa5d3c4de9767333c442ef2eb.tar.gz llvm-edc38a6cbd12a7cfa5d3c4de9767333c442ef2eb.tar.bz2 | |
[AMDGPU] Add option to pre-allocate SGPR spill VGPRs (#70626)
SGPR spill VGPRs are WWM registers so allow them to be allocated by
SIPreAllocateWWMRegs pass.
This intentionally prevents spilling of these VGPRs when enabled.
Diffstat (limited to 'flang/lib/Frontend/CompilerInvocation.cpp')
0 files changed, 0 insertions, 0 deletions