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| author | Brox Chen <guochen2@amd.com> | 2025-08-14 12:02:15 -0400 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-08-14 12:02:15 -0400 |
| commit | ec237da212a4d2a18ddb82486a8b4cb170e98319 (patch) | |
| tree | 8bde964aa4f3bdbf691107834836f3d7cd6a2781 /flang/lib/Frontend/CompilerInvocation.cpp | |
| parent | d57ab276b659c960fda8c0bb349648c4d266796e (diff) | |
| download | llvm-ec237da212a4d2a18ddb82486a8b4cb170e98319.zip llvm-ec237da212a4d2a18ddb82486a8b4cb170e98319.tar.gz llvm-ec237da212a4d2a18ddb82486a8b4cb170e98319.tar.bz2 | |
[AMDGPU][True16][CodeGen] insert proper register for 16bit data type in vop3p insts (#153143)
In true16 flow, we cannot simply replace v2f16 to its Lo16 when Lo == Hi
in a vop3p packed inst, since the register size is mismatched. This
trigger functional errors in the downstream branch and this is caused by
illegal `VGPR_32 = COPY VGPR_16` created by ISel and hit the rewrite
virtual reg and coalescer pass
Correctly insert reg_sequence/s_mov in true16 flow
Diffstat (limited to 'flang/lib/Frontend/CompilerInvocation.cpp')
0 files changed, 0 insertions, 0 deletions