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| author | Serge Pavlov <sepavloff@gmail.com> | 2021-03-19 20:10:01 +0700 |
|---|---|---|
| committer | Serge Pavlov <sepavloff@gmail.com> | 2021-04-21 12:55:30 +0700 |
| commit | d20a2376d8430a3043edb79bda98f2ef9bbca911 (patch) | |
| tree | 6626b7648554d977231a6e9d58a2c4ced6b6ba4b /flang/lib/Frontend/CompilerInvocation.cpp | |
| parent | d9806334d1a42a0338d4db703249d13108f1ef4d (diff) | |
| download | llvm-d20a2376d8430a3043edb79bda98f2ef9bbca911.zip llvm-d20a2376d8430a3043edb79bda98f2ef9bbca911.tar.gz llvm-d20a2376d8430a3043edb79bda98f2ef9bbca911.tar.bz2 | |
[RISCV] Introduce floating point control and state registers
New registers FRM, FFLAGS and FCSR was defined. They represent
corresponding system registers. The new registers are necessary to
properly order floating point instructions in non-default modes.
Differential Revision: https://reviews.llvm.org/D99083
Diffstat (limited to 'flang/lib/Frontend/CompilerInvocation.cpp')
0 files changed, 0 insertions, 0 deletions