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| author | Sander de Smalen <sander.desmalen@arm.com> | 2023-03-22 16:54:00 +0000 |
|---|---|---|
| committer | Sander de Smalen <sander.desmalen@arm.com> | 2023-03-24 14:37:16 +0000 |
| commit | c0d28d58fafe4480a129298efb36120170f35fa0 (patch) | |
| tree | 6892de8a03d0b279bcd2ecfc719412ad69d8aabb /flang/lib/Frontend/CompilerInvocation.cpp | |
| parent | 467ed2798772344e2a3b4a8d368575f1f9d1a8c6 (diff) | |
| download | llvm-c0d28d58fafe4480a129298efb36120170f35fa0.zip llvm-c0d28d58fafe4480a129298efb36120170f35fa0.tar.gz llvm-c0d28d58fafe4480a129298efb36120170f35fa0.tar.bz2 | |
[AArch64][SME] SelectSMETileSlice should also match to 'reg+0' when slice is ADD with non-constant RHS.
It would decompose an address into a `reg + 0` when the slice was not an ADD,
but when the RHS of the ADD was not a constant, it would simply not match.
This patch fixes that, by always resolving to a `reg + 0` slice.
Diffstat (limited to 'flang/lib/Frontend/CompilerInvocation.cpp')
0 files changed, 0 insertions, 0 deletions