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author | Benjamin Maxwell <benjamin.maxwell@arm.com> | 2023-08-23 09:04:55 +0000 |
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committer | Benjamin Maxwell <benjamin.maxwell@arm.com> | 2023-08-23 09:16:20 +0000 |
commit | 97da41418226bb426ae67b1e5b9c0ea3255042f2 (patch) | |
tree | 6265667e7caaf5e58172311bc30ed4ac6d2828eb /flang/lib/Frontend/CompilerInvocation.cpp | |
parent | ad35d916cd34154fd88757374d26491611f60cff (diff) | |
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[mlir][ArmSME] Lower loads/stores of (.Q) 128-bit tiles to intrinsics
This follows from D155306.
Loads and stores of 128-bit tiles have been confirmed to work in the
`load-store-128-bit-tile.mlir` integration test. However, there is
currently a bug in QEMU (see: https://gitlab.com/qemu-project/qemu/-/issues/1833)
which means this test produces incorrect results (a patch for this issue
is available but not yet in any released version of QEMU). Until a
fixed version of QEMU is available the integration test is expected to fail.
Reviewed By: c-rhodes, awarzynski
Differential Revision: https://reviews.llvm.org/D158418
Diffstat (limited to 'flang/lib/Frontend/CompilerInvocation.cpp')
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