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| author | SpencerAbson <Spencer.Abson@arm.com> | 2024-10-28 10:41:07 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-10-28 10:41:07 +0000 |
| commit | 64148944c56f50a50383c79d5b6d074d8608f2a4 (patch) | |
| tree | c982ecf82201a4c2ced59fc9346bde93d28c75cb /flang/lib/Frontend/CompilerInvocation.cpp | |
| parent | 09160a98218e7f1038e06c5d8e704a826ed0ae13 (diff) | |
| download | llvm-64148944c56f50a50383c79d5b6d074d8608f2a4.zip llvm-64148944c56f50a50383c79d5b6d074d8608f2a4.tar.gz llvm-64148944c56f50a50383c79d5b6d074d8608f2a4.tar.bz2 | |
[AArch64] Add assembly/disassembly for zeroing SVE2 integer instructions (#113473)
This patch adds assembly/disassembly for the following SVE2.2
instructions
- SQABS (zeroing)
- SQNEG (zeroing)
- URECPE (zeroing)
- USQRTE (zeroing)
- Refactor the existing merging forms to remove the now redundant bit 17
argument.
- In accordance with:
https://developer.arm.com/documentation/ddi0602/latest/
Diffstat (limited to 'flang/lib/Frontend/CompilerInvocation.cpp')
0 files changed, 0 insertions, 0 deletions