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| author | Sudharsan Veeravalli <quic_svs@quicinc.com> | 2025-04-02 12:14:50 +0530 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-04-02 12:14:50 +0530 |
| commit | 536fe74aaac437e147fc64dada6af8aab79a8b54 (patch) | |
| tree | 226dc78eed87041452da2840944aa15e710f80e6 /flang/lib/Frontend/CompilerInvocation.cpp | |
| parent | 09e19cfacfe5478a69f19014156deb384e5163c7 (diff) | |
| download | llvm-536fe74aaac437e147fc64dada6af8aab79a8b54.zip llvm-536fe74aaac437e147fc64dada6af8aab79a8b54.tar.gz llvm-536fe74aaac437e147fc64dada6af8aab79a8b54.tar.bz2 | |
[RISCV] Modify register type of extd* Xqcibm instructions (#134027)
The v0.8 spec specifies that rs1 cannot be x31 (t6) since these
instructions operate on a pair of registers (rs1 and rs1 + 1) with no wrap
around.
The latest spec can be found here:
https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.8.0
Diffstat (limited to 'flang/lib/Frontend/CompilerInvocation.cpp')
0 files changed, 0 insertions, 0 deletions