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author | Brox Chen <guochen2@amd.com> | 2024-11-22 12:12:13 -0500 |
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committer | GitHub <noreply@github.com> | 2024-11-22 12:12:13 -0500 |
commit | 4cc278587f3f44df08c6bebc0b4887f8522143f1 (patch) | |
tree | 04b5dc801f562a0bda2cdee78b4829208d0d8686 /flang/lib/Frontend/CompilerInvocation.cpp | |
parent | 9ea2a4aabe0902ee176f449825139e32642f4dd9 (diff) | |
download | llvm-4cc278587f3f44df08c6bebc0b4887f8522143f1.zip llvm-4cc278587f3f44df08c6bebc0b4887f8522143f1.tar.gz llvm-4cc278587f3f44df08c6bebc0b4887f8522143f1.tar.bz2 |
[AMDGPU][True16][MC] VOPC profile fake16 pseudo update (#113175)
Update VOPC profile with VOP3 pseudo:
1. On GFX11+, v_cmp_class_f16 has src1 type f16 for literals, however
it's semantically interpreted as an integer. Update VOPC class f16
profile from operand type f16, i16 to f16, f16, currently updating it
for fake16 format, and will update t16 format in the following patch.
2. 16bit V_CMP_CLASS instructions (V_CMP_**_U/I/F16) are named with
`t16`, but actually using 32 bit registers. Correct it by updating the
pseudo definitions with useRealTrue16/useFakeTrue16 predicates and
rename these `t16` instructions to `fake16`.
3. Update the inst select so that `t16`/`fake16` instructions are
selected in true16/fake16 flow.
4. The mir test file are impacted for a name change of these impacted 16
bit V_CMP instructions, but non-functional change to emitted code
Diffstat (limited to 'flang/lib/Frontend/CompilerInvocation.cpp')
0 files changed, 0 insertions, 0 deletions