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| author | Dhruv Chawla <dhruvc@nvidia.com> | 2024-05-16 08:08:06 +0530 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-05-16 08:08:06 +0530 |
| commit | 1dd0d3cf40f21b842dbee107b3d203db9fbaa4ae (patch) | |
| tree | b560af5931929c9744c74afa8a2c03717643ffac /flang/lib/Frontend/CompilerInvocation.cpp | |
| parent | 3a4c1b9b4428b08d4475decf74c11e0d328c5842 (diff) | |
| download | llvm-1dd0d3cf40f21b842dbee107b3d203db9fbaa4ae.zip llvm-1dd0d3cf40f21b842dbee107b3d203db9fbaa4ae.tar.gz llvm-1dd0d3cf40f21b842dbee107b3d203db9fbaa4ae.tar.bz2 | |
[AArch64][GISel] Fold COPY(y:gpr, DUP(x:fpr, i)) -> UMOV(y:gpr, x:fpr, i) (#89017)
This patch adds a peephole to AArch64PostSelectOptimize for codegen
that is caused by RegBankSelect limiting G_EXTRACT_VECTOR_ELT
only to FPR registers in both the input and output registers. This can
cause a generation of COPY from FPR to GPR when, for example, the
output register of the G_EXTRACT_VECTOR_ELT is used in a branch
condition.
This was noticed when looking at codegen differences between SDAG and GI
for the s1279 kernel in the TSVC benchmark.
Diffstat (limited to 'flang/lib/Frontend/CompilerInvocation.cpp')
0 files changed, 0 insertions, 0 deletions