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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-04-20 21:16:05 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-04-20 21:16:05 +0000 |
| commit | d14d2e7b185ffd7fcc171ea07734ba5b7aa73d8a (patch) | |
| tree | 4a53c2e74528b0d6f6225b8dcd90005dd2b9cc92 /clang/unittests/libclang/LibclangTest.cpp | |
| parent | 381b3d8aa372eb1df70530939b100d827df673c9 (diff) | |
| download | llvm-d14d2e7b185ffd7fcc171ea07734ba5b7aa73d8a.zip llvm-d14d2e7b185ffd7fcc171ea07734ba5b7aa73d8a.tar.gz llvm-d14d2e7b185ffd7fcc171ea07734ba5b7aa73d8a.tar.bz2 | |
[X86] Add WriteFSign/WriteFLogic scheduler classes
Split the fp and integer vector logical instruction scheduler classes - older CPUs especially often handled these on different pipes.
This unearthed a couple of things that are also handled in this patch:
(1) We were tagging avx512 fp logic ops as WriteFAdd, probably because of the lack of WriteFLogic
(2) SandyBridge had integer logic ops only using Port5, when afaict they can use Ports015.
(3) Cleaned up x86 FCHS/FABS scheduling as they are typically treated as fp logic ops.
Differential Revision: https://reviews.llvm.org/D45629
llvm-svn: 330480
Diffstat (limited to 'clang/unittests/libclang/LibclangTest.cpp')
0 files changed, 0 insertions, 0 deletions