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authorJay Foad <jay.foad@amd.com>2023-09-15 13:10:45 +0100
committerGitHub <noreply@github.com>2023-09-15 13:10:45 +0100
commit24a082878f7baec3651de56d54e5aa2b75a21b5f (patch)
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[update_mir_test_checks] Handle multiple defs of vreg (#66483)
When (post-SSA) MIR has multiple defs of the same vreg, update_mir_test_checks would use different variable names for each def like this, where DEF and DEF1 both refer to %0: ``` %0:gr32 = IMPLICIT_DEF %0:gr32 = IMPLICIT_DEF --> ; CHECK: [[DEF:%[0-9]+]]:gr32 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF1:%[0-9]+]]:gr32 = IMPLICIT_DEF ``` This should be harmless, but it messed up the way that mangle_vreg counts the number of names in vreg_map to come up with a new numeric suffix, such that you could get the same variable name for different vregs, like this, where DEF2 refers to both %0 and %2: ``` %0:gr32 = IMPLICIT_DEF %1:gr32 = IMPLICIT_DEF %0:gr32 = IMPLICIT_DEF %2:gr32 = IMPLICIT_DEF --> ; CHECK: [[DEF:%[0-9]+]]:gr32 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF1:%[0-9]+]]:gr32 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF2:%[0-9]+]]:gr32 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF2:%[0-9]+]]:gr32 = IMPLICIT_DEF ``` Fix this by always using the same variable name for the same vreg.
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