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| author | Jonas Paulsson <paulsson@linux.vnet.ibm.com> | 2018-05-24 08:38:06 +0000 |
|---|---|---|
| committer | Jonas Paulsson <paulsson@linux.vnet.ibm.com> | 2018-05-24 08:38:06 +0000 |
| commit | 7bcfeab4f2bc5c055103c63c47bc0ddece518489 (patch) | |
| tree | 6c12a86f4dda33ad3c75e315a7400ff6e5701923 /clang/unittests/Basic/VirtualFileSystemTest.cpp | |
| parent | f6b0c93fb3f6320efd8494866dee7da5c0b37143 (diff) | |
| download | llvm-7bcfeab4f2bc5c055103c63c47bc0ddece518489.zip llvm-7bcfeab4f2bc5c055103c63c47bc0ddece518489.tar.gz llvm-7bcfeab4f2bc5c055103c63c47bc0ddece518489.tar.bz2 | |
[ScheduleDAGInstrs / buildSchedGraph] Clear subregister entries also.
In addPhysRegDeps, subregister entries of the defined register were previously
not removed from Uses or Defs, which resulted in extra redundant edges for
subregs around the register definition.
This is principally NFC (in very rare cases some node got a different height).
This makes the DAG more readable and efficient in some cases.
Review: Andy Trick
https://reviews.llvm.org/D46838
llvm-svn: 333165
Diffstat (limited to 'clang/unittests/Basic/VirtualFileSystemTest.cpp')
0 files changed, 0 insertions, 0 deletions