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| author | QingShan Zhang <qshanz@cn.ibm.com> | 2020-03-13 07:25:55 +0000 |
|---|---|---|
| committer | QingShan Zhang <qshanz@cn.ibm.com> | 2020-03-13 07:28:28 +0000 |
| commit | d0fb34dc0967994b71e90351636215976279026a (patch) | |
| tree | c0684d0d5e2623fc7f65010c3f7fd64655fccab0 /clang/unittests/AST/SourceLocationTest.cpp | |
| parent | 09c8f38924d4bc302984de7bf67f4dbae15c38dc (diff) | |
| download | llvm-d0fb34dc0967994b71e90351636215976279026a.zip llvm-d0fb34dc0967994b71e90351636215976279026a.tar.gz llvm-d0fb34dc0967994b71e90351636215976279026a.tar.bz2 | |
[PowerPC] Replace the PPCISD:: SExtVElems with ISD::SIGN_EXTEND_INREG to leverage the combine rules
The PPCISD::SExtVElems was added by commit https://reviews.llvm.org/D34009. However,
we have another ISD node ISD::SIGN_EXTEND_INREG that perfectly match the semantics
of SExtVElems. And the DAGCombiner has some combine rules for SIGN_EXTEND_INREG
that produce better code.
Differential Revision: https://reviews.llvm.org/D70771
Diffstat (limited to 'clang/unittests/AST/SourceLocationTest.cpp')
0 files changed, 0 insertions, 0 deletions