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| author | Amara Emerson <amara@apple.com> | 2023-02-27 11:02:37 -0800 |
|---|---|---|
| committer | Amara Emerson <amara@apple.com> | 2023-02-27 11:24:24 -0800 |
| commit | 31d6a572579a5d1d9ae14a1a9d4ffbdb1b098e49 (patch) | |
| tree | 5b81f6dca231710da8c3a982e7006b83c18c26e9 /clang/tools/clang-format/clang-format-diff.py | |
| parent | 06daa515b27029885826833a5626937355abc4a1 (diff) | |
| download | llvm-31d6a572579a5d1d9ae14a1a9d4ffbdb1b098e49.zip llvm-31d6a572579a5d1d9ae14a1a9d4ffbdb1b098e49.tar.gz llvm-31d6a572579a5d1d9ae14a1a9d4ffbdb1b098e49.tar.bz2 | |
[AArch64][GlobalISel] Reorder stack up-adjustment and register copies
This change reorders the stack up-adjustment and return value copying phases of
machine-ir generation on Aarch64. Doing so prevents a bug observed for fastcc
calls with >8 arguments, where the up-adjustment required from making that call
is placed in the wrong place relative to spill and reloading code.
See: https://github.com/llvm/llvm-project/issues/60972 for full issue
reproduction and context.
Patch contributed by Bruce Collie
Differential Revision: https://reviews.llvm.org/D144791
Diffstat (limited to 'clang/tools/clang-format/clang-format-diff.py')
0 files changed, 0 insertions, 0 deletions